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SGI Origin & Onyx2 Patches 1998 May
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1998-04-01
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- 1 -
1. _P_a_t_c_h__S_G_0_0_0_2_7_5_4__R_e_l_e_a_s_e__N_o_t_e
This release note describes patch SG0002754 to IRIX 6.4
S2MP+OCTANE.
Patch SG0002754 replaces patches SG0002299, SG0002061,
SG0002036, SG0001956, SG0001965, SG0001887 and SG0001862.
1.1 _S_u_p_p_o_r_t_e_d__H_a_r_d_w_a_r_e__P_l_a_t_f_o_r_m_s
This patch contains bug fixes for Origin, Onyx2 and OCTANE
systems. The software cannot be installed on other
configurations.
1.2 _S_u_p_p_o_r_t_e_d__S_o_f_t_w_a_r_e__P_l_a_t_f_o_r_m_s
This patch contains bug fixes for IRIX 6.4 (version
1263561140). The software cannot be installed on other
configurations.
1.3 _B_u_g_s__F_i_x_e_d__b_y__P_a_t_c_h__S_G_0_0_0_2_7_5_4
This patch contains fixes for the following bugs in IRIX 6.4
S2MP+OCTANE. Bug numbers from Silicon Graphics bug tracking
system are included for reference.
+o Need a workaround for the bridge llp control register
bug (#454474): If the address in the register belongs
to the RESET_INT_STATUS, continue processing the
interrupt normally. In any other case this would be an
error due caused by software.
+o pciio_dmamap_done() doesn't work (Bug #460005): even
though calls to pciio_dmamap_done are being made,
subsequent calls to pciio_dmamap_addr still result in
complaints from the Hub support code about reuse of
mapping resources.
+o pciio_dmatrans_list() and pciio_dmamap_list() do not
work (Bug #462543): they always return NULL when
PCIIO_INPLACE is specified, after setting up
translations for all members of the input list and
replacing the first member of the list with the
translation of the last member.
+o Read Response Buffers not cleared when released
(#469217): If a device driver reduces its RRB
allocations after some DMA has occurred, it is possible
that it might leave the released RRB in a strange
state.
- 2 -
+o Need a way to explicitly clear RRBs (#469890): Some
devices under normal operation do strange things that
can leave RRBs in a confused state; the drivers for
these devices need a way to fix the situation.
+o pciio_dmatrans_list skips first byte (#473642): When
the PCIIO_NOSLEEP flag is specified in a call to
pciio_dmatrans_list, the first byte of the target is
discarded from the list.
+o Handle speculative stores to Prom space (#474335): The
R10000 CPU can emit a cache line writeback to any
address that will respond to a cache line read, due to
the way speculative stores are handled. Detect when
this happens to Prom space and recover.
+o Various enhancements in support of XIO-VME (#483978):
SGI's XIO-VME adapter uses a PCI bus internally, with
some enhancements; small changes were required to the
PCI infrastructure to allow the flexibility to take
advantage of these.
+o PCI Retry Counter bug workaround (#475347): Add a
workaround for a bug in Rev.C and earlier XIO-PCI
Bridge host adapter chips that can occasionally cause
PIO Stores to be dropped.
+o PCI BASE setup failure fix (#482338): handle PCI
devices with BASE regs that do not reset to all-zeros:
if the space that a window is decoding in is not
enabled in the COMMAND register, or indicates a decode
of PCI space that we do not allow, treat it as
unassigned.
+o Access to PCI I/O Spaces (#482741): PIO addresses
constructed to access device registers mapped in I/O
space encounter a hardware bug in XIO-PCI host adapters
until Rev D. Refuse to provide a mapping, rather than
providing a mapping that does not work.
+o Data corruption with old chips, raw DMA (#482836):
Prevent data corruption that may occur if the
prefetcher on a Rev B XIO-PCI host adapter chip is
enabled and the QL SCSI initiates DMA that is not
cache-line aligned.
+o PCI External Address Translation bug workaround
(#484930): If the system is updating some external
ATEs in the PCI host adapter while DMA on that bus is
using another external ATE, the DMA may be directed
using stale ATE information, resulting in the DMA
- 3 -
fetching from or storing to the wrong page of physical
memory.
+o Unable to control endianness of PCI PIO (#486476): The
PCIIO_BYTE_STREAM and PCIIO_WORD_VALUES flags were
being ignored by all pciio_pio functions.
+o Insufficient PIO mapping resources (#486479): Certain
resources previously reserved for PCI slots that had no
devices attached may now be used to satisfy PIO
requests for other slots.
+o PCI Expansion Roms not handled (#486481): Add code to
allocate PCI address space for Expansion Roms, and to
support PCIIO_SPACE_ROM in PIO requests as a request to
map the space allocated to the ROM.
+o Revised PCI Bus Access driver (#486484,#485281): Added
a loadable device driver (pciba) that provides direct
access to the PCI Bus and the devices on it.
+o Support access to IOC3 in pciba (#491100): SGI's IOC3
device is somewhat unique in that it uses two pairs of
PCI REQ/GNT lines. The pciba driver has been revised
to allow access to the IOC3 using the secondary slot.
+o Change pciba behavior with misaligned windows
(#491837): Change vague warning that always appears
into a specific recommentdation, only printed in debug
kernels. Additionally, do not allow mmap operations to
misaligned windows.
+o Allow PCIIOCSETULI from 32-bit apps (#502808): The
parameter structure for ULI work contains pointers, and
therefore looks different when the call is made from a
32-bit application. Detect the difference and do the
right thing.
+o Deliver sys/PCI/pciba.h (#507789): A previous version
of this patch introduced the pciba driver. The header
file defining values for IOCTL commands for this driver
was not included in the patch; now it is.
+o Avoid crashing when pciba ioctl encounters an error
(#509712): pciba_ioctl was disconnecting an interrupt
handle that was really an uninitialized automatic
variable, causing an immediate crash in
pcibr_intr_disconnect.
+o Provide byte-[un]swapped PIO access (#511650): PIO
access to the PCI bus using mmap facilities in the
- 4 -
pciba driver always set up the byte swappers assuming
the device on the other end was little-endian. After
this patch, additional verticies will be built with _be
and _le suffixes; mmap-provided pointers from these
verticies will explicitly be set up for big-endian and
little-endian targets.
+o Document hwo to load pciba at system startup (#511653):
The manual page for pciba has been revised to contain
explicit directions on how to configure the system so
that the pciba driver is loaded automatically during
boot.
+o Handle PIO timeouts to unknown PCI addresses (#511664):
If an access was made to the PCI bus at an address that
did not correspond strictly with a region decoded by a
device's BASE register, the resulting diagnosis was
extremely confusing to deal with. This patch adds more
smarts to the address search algorithms, and makes the
message when there is no match much simpler to
understand.
+o Report PCI host adapter revisions to the log (#511695):
Subtile differences between various revisions of the
PCI host adapter chip are important when diagnosing
problems in the system. With this patch, all kernels
linked for debugging will print the revisions of such
chips into the system log at boot time.
+o PCI interrupts stop when one handler disconnects
(#511698): Shared interrupt was getting disabled when
any handler disconnects from it, preventing other
handlers from being notified should that interrupt
occur again later; This has been fixed.
+o Base registers are not being initialized properly
(#544777): Pci base register setting code assumes that
the base registers are contiguous which is not always
true. This has been fixed.
+o Dma alenlist address translation interfaces donot reset
cursor (#555051): Pciio_dma{trans,map}_list interfaces
now reset the internal cursor of the alenlist of pci
addresses. Also the error dumping code prints out the
SSRAM parity error register during a PMU_ESIZE fault.
+o Pci space checking for MEM not fully correct in pio
error handling (#558198): In the pio error handling
path fixed the MEM space comparison to find out a
possible base register mapping the pio address for the
device. Basically if the mem space is either MEM32 or
- 5 -
MEM64 at the time of base register mapping space
comparison the one for the base register is being
converted to MEM (in the case of MEM32 or MEM64)
whereas the raw space for the pio error address is
still being left as MEM32 or MEM64 causing the pci
device error handler not being called.
+o hang when re-using large dmamaps (#571536): Any
application will hang when re-using a dmamap that is
large enough to be forced into the external ATEs in the
XIO-VME bridge.
1.4 _S_u_b_s_y_s_t_e_m_s__I_n_c_l_u_d_e_d__i_n__P_a_t_c_h__S_G_0_0_0_2_7_5_4
This patch release includes these subsystems:
+o patchSG0002754.eoe1_sw.unix
1.5 _I_n_s_t_a_l_l_a_t_i_o_n__I_n_s_t_r_u_c_t_i_o_n_s
Because you want to install only the patches for problems
you have encountered, patch software is not installed by
default. After reading the descriptions of the bugs fixed
in this patch (see Section 1.3), determine the patches that
meet your specific needs.
If, after reading Sections 1.1 and 1.2 of these release
notes, you are unsure whether your hardware and software
meet the requirements for installing a particular patch, run
_i_n_s_t. The _i_n_s_t program does not allow you to install
patches that are incompatible with your hardware or
software.
Patch software is installed like any other Silicon Graphics
software product. Follow the instructions in your _S_o_f_t_w_a_r_e
_I_n_s_t_a_l_l_a_t_i_o_n _A_d_m_i_n_i_s_t_r_a_t_o_r'_s _G_u_i_d_e to bring up the miniroot
form of the software installation tools.
Follow these steps to select a patch for installation:
1. At the Inst> prompt, type
iiiinnnnssssttttaaaallllllll ppppaaaattttcccchhhhSSSSGGGG_x_x_x_x_x_x_x
where _x_x_x_x_x_x_x is the patch number.
2. Initiate the installation sequence. Type
IIIInnnnsssstttt>>>> ggggoooo
- 6 -
3. You may find that two patches have been marked as
incompatible. (The installation tools reject an
installation request if an incompatibility is
detected.) If this occurs, you must deselect one of
the patches.
IIIInnnnsssstttt>>>> kkkkeeeeeeeepppp ppppaaaattttcccchhhhSSSSGGGG_x_x_x_x_x_x_x
where _x_x_x_x_x_x_x is the patch number.
4. After completing the installation process, exit the
_i_n_s_t program by typing
IIIInnnnsssstttt>>>> qqqquuuuiiiitttt
1.6 _P_a_t_c_h__R_e_m_o_v_a_l__I_n_s_t_r_u_c_t_i_o_n_s
To remove a patch, use the _v_e_r_s_i_o_n_s _r_e_m_o_v_e command as you
would for any other software subsystem. The removal process
reinstates the original version of software unless you have
specifically removed the patch history from your system.
vvvveeeerrrrssssiiiioooonnnnssss rrrreeeemmmmoooovvvveeee ppppaaaattttcccchhhhSSSSGGGG_x_x_x_x_x_x_x
where _x_x_x_x_x_x_x is the patch number.
To keep a patch but increase your disk space, use the
_v_e_r_s_i_o_n_s _r_e_m_o_v_e_h_i_s_t command to remove the patch history.
vvvveeeerrrrssssiiiioooonnnnssss rrrreeeemmmmoooovvvveeeehhhhiiiisssstttt ppppaaaattttcccchhhhSSSSGGGG_x_x_x_x_x_x_x
where _x_x_x_x_x_x_x is the patch number.
1.7 _K_n_o_w_n__P_r_o_b_l_e_m_s